FPGA_ASIC-FPGA时钟分配网络设计技术

这篇文章论述了用于FPGA的可优化时钟分配网络功耗与面积的时钟布线模型。并在时钟分配网络中引入数字推延镜像相环时钟误差，探讨了FPGA时钟网络中锁相环的终结方案

(This article discusses a clock routing model for FPGAs that optimizes power and area for clock distribution networks. And the digital delay mirror phase loop clock error is introduced into the clock distribution network, and the termination scheme of the phase-locked loop in the FPGA clock network is discussed.)

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